1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to substrate diodes of complex SOI circuits, which may be used for thermal sensing application and the like.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the latter aspect renders the reduction of the channel length, and associated therewith the reduction of the channel resistivity, a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
In view of the former aspect, in addition to other advantages, the SOI (semiconductor or silicon on insulator) architecture has continuously been gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues. Contrary to the body of bulk devices, which is electrically connected to the substrate and thus applying a specified potential to the substrate maintains the bodies of bulk transistors at a specified potential, the body of SOI transistors is not connected to a specified reference potential, and, hence, the body's potential may usually float due to accumulating minority charge carriers, unless appropriate countermeasures are taken.
A further issue in high performance devices, such as microprocessors and the like, is an efficient device-internal temperature management due to the significant heat generation. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance.
Typically, for thermal sensing applications, an appropriate diode structure may be used wherein the corresponding characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may therefore typically be desirable to provide a substantially “ideal” diode characteristic in order to provide the potential for precisely estimating the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is typically formed in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements. Thus, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures, without undue negative effects on the actual circuit elements.
However, during the process flow for manufacturing the substrate diode, a plurality of process steps have to be performed that are specifically designed for the substrate diode, wherein one of these process steps includes a high energy implantation process for defining a well region for the substrate diode, which may result in a reduced ideality of diode characteristics, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 representing an SOI device. The device 100 comprises a substrate 101 which includes, at least in an upper portion thereof, a substantially crystalline substrate material which may be referred to as substrate semiconductor layer 102, which may represent the pre-doped material according to standard SOI substrates. For instance, the substrate semiconductor layer 102 may have incorporated therein a moderately low concentration of a P-type dopant. Furthermore, the semiconductor device 100 comprises a buried insulating layer 104, for instance, comprised of silicon dioxide and the like, which separates a semiconductor layer 105, such as a silicon layer, from the substrate semiconductor layer 102. The semiconductor layer 105 may be comprised of a substantially crystalline semiconductor material, such as silicon, silicon/germanium or any other appropriate silicon-based material for forming therein and thereon a plurality of circuit elements, such as transistors and the like. For this reason, the semiconductor layer 105 may also be referred to as an “active” semiconductor layer. Moreover, the semiconductor device 100 may comprise a first device region 110, dedicated to receiving a substrate diode in a later manufacturing stage, and a second device region 120, which comprises a plurality of trench isolation structures 121. The isolation structures 121 may be comprised of any appropriate material, such as silicon dioxide and the like.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After providing the substrate 101 having formed thereon the buried insulating layer 104 and the active semiconductor layer 105, the device 100 may be prepared for a subsequent etch process for forming respective trench openings for the trench isolation structures 121. For this purpose, a hard mask layer, also used as a chemical mechanical polishing (CMP) stop layer (not shown), may be formed, for instance, in combination with an etch stop liner (not shown), above which an appropriate etch mask may be created on the basis of sophisticated lithography techniques. Thereafter, the trench openings may be etched to extend to the buried insulating layer 104 followed by an appropriate re-filling of the trench openings, for instance, on the basis of well-established oxidation and deposition techniques. Thereafter, any excess material may be removed by chemical mechanical polishing using the stop layer for controlling the process and subsequently removing residues of the CMP stop layer using the etch stop layer, which may then also be removed, if desired.
FIG. 1b schematically illustrates the semiconductor device 100 during an implantation process 130, which is performed on the basis of an implantation mask 131 covering the second device region 120 and exposing at least a portion of the first device region 110. The implantation process 130 is designed such that an appropriate species, such as an N-type species, is introduced into the substrate semiconductor layer 102 in order to define a well region 111 for a substrate diode to be formed in a later manufacturing sequence. For this purpose, the process parameters of the implantation process 130 have to be selected such that the dopant ions pass through the active layer 105, the buried insulating layer 104 and into the substrate semiconductor layer 102 according to a specified distribution and depth. Hence, a moderately high degree of variability may occur during the implantation process 130, thereby creating a respective variability of the diode characteristics, which may thus translate into a reduced reliability in detecting the thermal conditions in the substrate 101. Furthermore, since moderately high implantation energies are required, a double-ionized dopant species may have to be used, thereby resulting in significantly reduced implantation currents, thus contributing to increased process times for the process 130. Consequently, the throughput of respective implantation tools is significantly reduced.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, the second device region 120 comprises a plurality of schematically depicted gate electrode structures 122, while also in this stage drain and source extension regions 123 may have been formed. Furthermore, an etch mask 132 is provided which covers the second device region 120 while exposing the first device region 110 to an etch ambient 133. The etch ambient 133 is configured to etch through the active semiconductor layer 105 and the buried insulating layer 104 in order to expose the well region 111, thereby forming respective substrate openings 112A, 112B. During the moderately complex etch process 133, which requires different etch chemistries for etching through the layer 105 and the buried insulating layer 104, the exposure of the well region 111 and thus attack and removal of material thereof may also affect the diode characteristics, so that, in combination with the preceding high energy implantation process 130 of the overall device, stability of the substrate diode still to be formed may be deteriorated.
After exposure of the well region 111 by means of the substrate openings 112A, 112B, the further processing may be continued by completing respective transistor structures on the basis of the gate electrodes 122, while, in the same process sequence, the highly doped areas for the substrate diodes may also be formed. That is, when forming respective N-type drain and source regions, one of the openings 112A, 112B may be masked while the other one may also receive a respective high dopant concentration. Similarly, when P-type drain and source regions are formed in the second device region, the other one of the openings 112A, 112B is masked. Thus, a respective contact area and a diode PN junction may be provided, which may then be contacted during a common manufacturing sequence, in which contacts are also formed to the transistor structures in the second device region.
Thus, as previously explained, reduced uniformity and thus decreased diode ideality may result from the process sequence described above, wherein a reduced overall throughput may also be caused due to the high energy implantation process.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.